Altium

Design Rule Verification Report

Date:		9/4/2025
Time:		2:46:55 PM
Elapsed Time:		00:00:01
Filename:		C:\Users\Marc Pirello\Altium Marc\Solutions\ISC - PCIe Duotone\PCIe_Duotone_V3\PCIe_Duotone.PCBDOC

Warnings:		0
Rule Violations:		0

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=3mil) (All),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Modified Polygon (Allow modified: No), (Allow shelved: No)	0
Width Constraint (Min=3mil) (Max=200mil) (Preferred=10mil) (All)	0
Routing Layers(All)	0
Routing Via (MinHoleWidth=10mil) (MaxHoleWidth=10mil) (PreferredHoleWidth=10mil) (MinWidth=19mil) (MaxWidth=19mil) (PreferedWidth=19mil) (WithinRoom('FPGA'))	0
Routing Via (MinHoleWidth=6mil) (MaxHoleWidth=78.74mil) (PreferredHoleWidth=10mil) (MinWidth=12mil) (MaxWidth=78.74mil) (PreferedWidth=20mil) (All)	0
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)	0
Hole Size Constraint (Min=6mil) (Max=236.22mil) (All)	0
Pads and Vias to follow the Drill pairs settings	0
Hole To Hole Clearance (Gap=8mil) (All),(All)	0
Minimum Solder Mask Sliver (Gap=4mil) (All),(All)	0
Net Antennae (Tolerance=0mil) (All)	0
Matched Lengths(Tolerance=1mil) (InDifferentialPair('PCIE.PCIE_CLK'))	0
Matched Lengths(Tolerance=7mil) (InDifferentialPair('PCIE.PCIE_TX0'))	0
Matched Lengths(Tolerance=7mil) (InDifferentialPair('PCIE.PCIE_RX0'))	0
Total	0